Types of Memory
There exist different types of non-volatile memory. Read-only memory (ROM) is programmed at the time of manufacturing. They are cheap to produce but the content of their cells cannot be changed. The memory cells of programmable ROMs (PROMs) can be programmed once, typically using a voltage higher than the operational voltage, but not be erased again. In an erasable PROM (EPROM), all cells can be erased together by exposing the memory cells to relatively strong UV radiation. The cells of electronically erasable PROMs (EEPROMs) and flash EEPROMs can be programmed and erased electronically. While in EEPROMs, every memory cell must be erased individually, in flash EEPROMs, all memory cells or large blocks of cells can be erased together (in a flash).
Despite their higher prices compared with RAM and ROM, EEPROMs are becoming more and more popular. They allow the replacement of code stored in a memory module of a device without the need to remove that memory module from the device. Unlike RAM, they also allow the ability to maintain the stored data in the absence of a supply voltage. In addition, they are also insensitive to mechanical stress and magnetic fields. For these reasons, memory cards based on EEPROMS have also become a popular storage media in mobile applications. Examples of such applications are personal media players or mobile phones.
Floating Gate Memory Cells
There are different types of EEPROM cells. Several types are based on floating gate MOSFETs (metal oxide semiconductor field effect transistors). Between a control gate and a source/drain channel, a conductive layer, the floating gate, is sandwiched between two insulating layers. Charge is brought onto the floating gate using hot electron injection or Fowler-Nordheim tunneling. A memory cell containing a significant amount of charge on its floating gate is referred to as programmed and represents a logical “1”. As a consequence of the resulting electrical field, the substrate below the gate is depleted of charge carriers and the channel resistance increases for a constant control gate voltage. Inversely, floating gate MOSFETs, which contain no or only little charge on the floating gate, are called erased and have a higher conductivity representing a logical “0”.
Variations of the floating gate memory cell exist, in which different amounts of charge are stored in the floating gate. The resulting different channel conductivity is used to encode two or more bits of information. For example, a memory cell providing four different states of charge or channel conductivity can be used to store two bits of information.
NROM Memory Cells
Another type of memory cell is based on nitride ROMs (NROMs). NROM cells comprise a dielectric, non-conductive layer between the control gate and the source/drain channel of the substrate. Typically, a nitride layer is sandwiched between two oxide layers, with the resulting memory device called an ONO EEPROM.
Unlike in the case of a conductive floating gate, charge trapped in the dielectric layer of an NROM memory cell remains fixed in this layer. Consequently, charge can be stored in different locations of the dielectric layer, e.g., close to a source or drain terminal of a MOSFET.
As with a conductive floating gate transistor, the amount of charge trapped and thus the conductivity of the channel underneath it can be divided into several levels for an NROM memory cell, allowing several bits of information to be stored.
Alternatively, charge can be stored in different regions of the nitride layer, with each region acting as a different storage cell. From the U.S. Pat. No. 6,011,725, which is incorporated herein by reference, it is known to store a first bit near a first terminal of the NROM cell, for example the source, and to store a second bit near the second terminal of the cell, for example the drain. As is known in the art, the first bit can be read by measuring a forward current through the NROM cell, and the second bit can be read by measuring a backward current through the NROM cell.
Storing two bits of information in different regions of the nitride layer has the advantage that the difference between the individual states can be detected easier than in a multi-level memory cell. However, the state of the second bit influences the current flowing through the cell when detecting the state of the first bit and vice-versa. This is also referred to as the second bit effect. Though the second bit effect is small in comparison with the effect caused by the state of the bit to be read, it can become more important as the operational voltage of the memory cell becomes lower.
Low Voltage Circuits and Sensing Amplifiers
In order to save power and to allow smaller die structures to be used for a semiconductor circuit, the operational voltages of memory modules are getting lower and lower. Whereas 5 V and 3.3 V were previously used as supply voltages, new devices use voltages of 1.6 V for example.
Sensing arrangements known in the art usually sense a threshold control gate voltage, at which a fixed reference current flows through a memory cell to be sensed. Voltage drops occurring at the various lines of an integrated circuit arrangement reduce the signal strength to be detected. Most importantly supply and bit lines connecting a memory cell with a sense amplifier and other periphery devices have an associated resistance over which a voltage drops. Consequently, the voltage observed by the sensing arrangement is not equal to the local voltage of the memory cell. The higher the current flowing through the cell, the higher is the voltage drop over the bit line.
The bit line connecting the memory cell with a sense amplifier also has an associated capacitance. Consequently, signal changes of the sense amplifier to a predefined voltage level do not occur instantaneously at the memory cell and vice-versa. Instead, the voltage of the bit line increases over time, like the voltage of a charging capacitor. This might cost valuable energy of a high voltage source being used to charge the bit line before or during sensing. In order to enable high operation speed of the memory device, a high current must be provided to charge or discharge the bit line. If the bit line is discharged over the memory cell for sensing, the relatively small current flowing through a memory cell can result in a lengthy sensing phase, which limits the overall performance of the memory device.
The adverse properties of the bit line contribute even more to differential sense amplifiers, i.e., sense amplifiers that compare a signal obtained from the memory cell to be sensed with a signal obtained from a reference cell in a known state. In such an arrangement, a second bit line must be provided between the sense amplifier and the reference cell, which causes further voltage drops or capacitance to the sense network.